1. Field of the Invention
This invention relates to equipment to test the electrical properties of integrated circuits. More particularly, the invention relates to a space transformer that is positioned between a test probe head and a printed circuit board in a vertical pin probing device.
2. Description of the Related Art
Integrated circuits are typically formed as a plurality of chips having circuit traces and other features formed by photolithography on a surface of a silicon or gallium arsenide wafer. The chips are then singulated and encased within an electronic package for use in a wide range of applications. Since the electronic package is frequently contained within an expensive piece of equipment, it is desirable to verify the electrical properties of the circuit traces prior to singulation. The circuit traces are electrically tested for electrical properties such as continuity and short circuits. As disclosed in U.S. Pat. No. 6,661,244, which is incorporated by reference in its entirety herein, one method of testing the integrated circuit is with a vertical pin probing device.
A portion of a vertical pin probing device as known from the prior art is illustrated in FIG. 13. A device under test 14, typically an integrated circuit, is supported by a movable chuck 16. The device under test 14 is positioned under a vertical pin integrated circuit probe at assembly 18, which includes a first die 20 having a first array of holes 21 spaced from a second die 22 having a second array of holes 23. A spacer 24 separates the first die 20 from the second die 22. Probe pins 26 extend through both the first array of holes 21 and the second array of holes 23. A probe tip end 26a contacts a portion of the device under test 14 while an opposing second end 26b of the probe pin extends outward from the second array of holes 23. The first array of holes 21 and second array of holes 23 are slightly offset from one another and the probe pins are curved in a snake-like configuration to promote buckling so as to create a substantially uniform contact pressure on the integrated circuit device under test 14 despite any slight vertical unevenness or misalignment.
The prior art space transformer 29, partially illustrated in FIG. 13, includes a mounting block 30 with a third array of holes 34 that align with the second end 26b of the probe pin 26. A wire 36 extends into the third array of holes 34 to make electrical contact with the second end 26b of probe pin 26.
With reference to FIG. 14, the wire 36 is fixedly held in place in a well 32 of the mounting block 30 by an epoxy potting compound 39. The well 32 is fastened 38 to a printed circuit board 10 having conductive traces 12 formed on at least one surface. The wires 36 are soldered to the conductive traces 12 providing electrical interconnection to the device under test 14 by way of the probe pins 26.
There are a number of problems with the prior art space transformer. Aligning and soldering each individual wire 36 is time-consuming and expensive. The flatness of the mounting block 30 is impacted by both the fasteners 38 and epoxy potting compound 39. If the mounting block is offset or distorted, electrical continuity between the device under test and the circuit traces on the printed circuit board may be lost. There remains, therefore a need for a lower cost and more reliable space transformer that does not suffer from the above-named disadvantages.